Microprocessors commonly include protocols for transferring data across a processor bus to other units of a system. In particular, the Pentium® class microprocessors sold by the Intel Corporation of Santa Clara, Calif. have a well-defined front side bus interface protocol.
FIG. 1 illustrates a prior art processor cluster 100 for Pentium® class microprocessors. The processor cluster 100 refers to one or more processors that reside on the Pentium® front side bus 115 (e.g., typically one to four processors), which is illustrated in the example of FIG. 1 as the “Pentium Pro Bus” line. Other components, such as a main memory 120 and one or more bridges 130, may be coupled to bus 115. A bridge 130 may, in turn, act as a surrogate for addressing other entities coupled to the bridge. An individual bridge 130 may, in turn be coupled to other buses 140, such as peripheral component interconnect (PCI) buses which in turn may be coupled to other bridges 150 and buses. Other components, such as an advanced programmable interrupt controller (APIC) 190 and an APIC bus 195 may also be included in processor cluster 100.
There is a well-defined front side bus protocol for Pentium class processors, which is described in the book entitled “Pentium® Pro and Pentium® II System Architecture”, second edition, chapters 8–17, by Tom Shanley, Addison-Wesley (1998), the contents of which are hereby incorporated by reference. Each CPU 110 includes a front side bus interface. Additionally, other modules coupled to the front side bus 115, such as bridge 130, also include a corresponding front side bus interface.
A front side bus interface may include three types of agents: a request agent that initiates a transaction (a transaction initiator); a response agent, which is the target of a transaction; and a snoop agent, which snoops snoop caches of target devices. FIG. 2 illustrates bus signals entering and leaving a bus agent 200. The signals may include snoop phase signals 205, request phase signals 210, response phase signals 215, data phase signals 220, and error phase signals 225. Each signal group is used during a particular phase of the transaction.
The Pentium® front side bus 115 is a pipelined bus with in-order data movement. A defer mechanism allows for a limited amount of reordering of data movement. However, the defer mechanism increases overhead and is therefore often not used. Thus, typically once a transaction is initiated, the transaction phases proceed in a predefined order. For the Pentium Pro®, these include: an arbitration phase for an agent to gain access to the bus, a request phase for an initiating agent to issue a transaction request to a target, an error phase (e.g., a parity bit check by a request agent to determine if a request was received without error), a snoop phase for a the request agent to snoop the snoop cache of targets, a response phase for a target to deliver a response regarding how it will reply to a request, and a data phase for a data transfer associated with an accepted transaction to take place (e.g., a read or a write operation between the initiator and the target).
FIG. 3 illustrates an exemplary sequence 300 of pipelined transactions for a Pentium® front side bus interface. Since there is pipelined in-order execution of transactions, each new transaction that is scheduled cannot complete its data phase until the previous transaction has completed its data phase. However, the data phase of a transaction may be stretched out if the request and response agents are not ready to transfer the data. Thus, for example, a data phase 305 on one transaction may be stretched out compared to other transactions if, for example, the response agent is not immediately ready to transfer data.
A drawback of such a front side bus interface is that transactions can become stalled waiting for previous transactions to complete their data phase. For example, a data phase 310 of one transaction can become stalled because of a stretched out data phase 305 of a previous transaction. In some applications this can result in excessive latency for completing transactions. Additionally, since all transaction requests are scheduled and execute in-order, a stretched out data phase of a comparatively low-priority transaction can stall the completion of a higher-priority transaction. Additionally, in a bridge 130 coupled to two or more other entities, a stretched out data phase for a transaction addressed to one of the entities can stall transactions addressed to the other entity.
A front side bus is one example of a pipelined bus in which transactions can become stalled waiting for previous transactions to complete their data phase. More generally, other types of buses with similar principles of operation may experience similar problems.
Therefore, what is desired is an improved data management technique for a pipelined bus interface unit.